1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (hereinafter, referred to as CMOS) device having an n-channel and a p-channel metal oxide semiconductor field effect transistors (or n-channel and p-channel MOSFETs) and manufacturing method of the same, more particularly to a CMOS device and manufacturing method thereof capable of restraining short channel effect of the n-channel and p-channel MOSFETs without increasing the number of photolithography processes.
2. Description of the Related Art
In general, when a gate length of a device is made short by critical dimension of the device, a threshold voltage may decrease or a short channel effect may remarkably arise. In one of the methods for restraining the short channel effect, there has been known that a source and drain region should be made shallow. However, in case of making the source and drain region shallow, there arise problems such that the process margin of device becomes narrow when forming a contact on the source and drain region. Further, it is difficult to make the silicide regions, and the source and drain regions are usually formed as an LDD (Lightly Doped Drain) structure, that is, the regions are formed by a low impurity concentration region having a shallow junction and a high impurity concentration region having a relatively deep junction.
This improves a short channel effect by the low impurity concentration region having the shallow junction and also permits the silicide formation and makes contact easy by means of the high impurity concentration region having the relatively deep junction. However, in order of forming both an n-channel MOSFET (hereinafter, referred to as nMOSFET) and a p-channel MOSFET (hereinafter, referred to as pMOSFET) as an LDD structure by an ordinary manufacturing method, a well region opposite to a substrate should be coated by a mask at each of the processes such as (1) form of n-type low concentration region, (2) form of p-type low concentration region, (3) form of n-type high concentration region and (4) form of p-type high concentration region, thus, the photolithography process must be carried out four times repeatedly to form a source and drain region, requiring a large number of process steps. Therefore, a method has been proposed that a pMOSFET should be fabricated with a single drain structure from which the short channel effects are not significant, and in which a source and drain region is formed only by two photolithography processes such a system is described with reference to the drawings below.
FIGS. 3(a) to 3(f) are sectional views of a device showing a manufacturing processes. As shown in FIG. 3(a), a field oxidation film 102 is formed on a p-type Si (Silicon) substrate 101 to form an n-type well region 103 and a p-type well region 104.
Thereafter, a gate oxidation film 105 is formed on the p-type Si substrate 101, as shown in FIG. 3(b), a gate electrode 106 of an nMOSFET and a gate electrode 107 of a pMOSFET both made of polysilicon are then formed.
Thereafter, As.sup.+ (arsenic ion) 108 is ion-implanted onto an nMOSFET forming region and a pMOSFET forming region in low concentration (ex. 2 to 5.times.10.sup.13 cm.sup.-2 in dose) to form n-type low concentration regions 109 and 110 in both the nMOSFET forming region and the pMOSFET forming region as shown in FIG. 3(c).
As shown in FIG. 3(d), after forming an SiO.sub.2 layer on the p-type Si substrate 101 by CVD (Chemical Vapor Deposition) method, the anisotropic etching process is applied thereto to form side-wall spacers 111 and 112 composed of SiO.sub.2 on the side surfaces of gate electrodes 106 and 107 of nMOSFET and pMOSFET, respectively.
As shown in FIG. 3(e), after the nMOSFET is coated by a first mask layer 113 as a photoresist, B.sup.+ (boron ion) 114 is ion-implanted onto the pMOSFET forming region in high concentration to thereby form a p-type high concentration source and drain region 115. At this time, the n-type low concentration region 110 is contained in the p-type high concentration source and drain region 115 to be inverted to a p-type region. After removing the first mask layer 113, as shown in FIG. 3(f), the pMOSFET region is coated by a second mask layer 117 as a photoresist, and As.sup.+ 118 is ion-implanted onto the nMOSFET region in high concentration to form an n-type high concentration region 119. The second mask layer 117 is then removed, completing the manufacturing processes of a CMOSFET.
In addition, other CMOS devices and manufacturing methods have proposed such that an nMOSFET should only be made into the LDD structure while both an nMOSFET and a pMOSFET should be made into the LDD structure.
That is, The document of Japanese Laid-Open Patent Application No. Hei3-41763 discloses the following process: a gate electrode is formed on an nMOSFET forming region and a pMOSFET forming region and n.sup.- -type region is formed in the nMOSFET forming region with a resist film coated on the pMOSFET forming region; side-wall spacers are formed on the side surfaces of gate electrode for the nMOSFET and an n-type impurity is doped into the nMOSFET forming region in high concentration to form an n.sup.+ -type region with a resist film coated on the pMOSFET forming region; and other side-wall spacers, width of which is wider than that of nMOSFET, are formed on the side surfaces of gate electrode of the pMOSFET forming region and a p-type impurity is doped into the pMOSFET forming region in high concentration to form a p.sup.+ -type source and drain region with a resist film coated on the nMOSFET forming region.
While the document of Japanese Laid-Open Patent Application No. Hei5-145030 discloses the following process: a gate electrode is formed on an nMOSFET forming region and a pMOSFET forming region, an n-type impurity is doped into both the regions in low concentration to form an n-type region on both the regions, and side-wall spacers are formed on the side surfaces of both the gate electrodes; a p-type impurity is ion-implanted onto the pMOSFET forming region in high concentration with a resist film coated on the nMOSFET to form a p.sup.+ -type region on the pMOSFET forming region; subsequently, the p-type impurity is ion-implanted thereon in an inclined direction to thereby invert the n.sup.- -type region to a p.sup.- -type region; and the n-type impurity is doped into the nMOSFET forming region in high concentration with a resist film coated on the pMOSFET to form an n.sup.+ -type region.
According to the examples described above, the nMOSFET is formed of the LDD structure while the pMOSFET is formed of the single drain structure as shown in FIG. 3 (f). However, since the short channel effect depends on a junction depth of the source and drain regions located close to the channel region in general, in the examples described above, the nMOSFET region is controlled by the short channel characteristic depending on a junction depth of the n-type low concentration region 109 and the pMOSFET region is controlled by that characteristic depending on a junction depth of the p-type high concentration source and drain region 115. Therefore, since the n-type low concentration region 109 should remain to a certain extent in the nMOSFET forming region, it is desirable that the side-wall spacers 111, which become masks in the ion-implantation of As.sup.+ shown in FIG. 3(f), are formed thick in consideration of the width in a lateral direction of the n-type high concentration region 119. However, since the pMOSFET side is used by the process to be inverted by the ion-implantation of B.sup.+ as shown in FIG. 3(e) after forming a conductive type of the n-type low concentration region as side-wall spacers, the p-type high concentration source and drain region should be formed to some extent of depth in case of forming the side-wall spacers in thick. To this end, the junction depth of the p-type high concentration source and drain region in the pMOSFET region becomes deeper than that of the n-type high concentration source and drain region in the nMOSFET region. As a result, the short channel effect of the pMOSFET becomes remarkable, so that the critical dimension of the gate length for the pMOSFET is limited.